1. Field of the Invention
The present invention generally relates to semiconductor device fabrication and more specifically to the fabrication of transistors with low thermal budget.
2. Description of the Related Art
Transistors are widely used in electronic circuits. A typical metal oxide semiconductor (MOS) transistor, for example, has a gate, a source, and a drain that are formed in a semiconductor substrate. FIGS. 1A-1E illustrate the basic process sequence for fabricating a p-channel MOS transistor in accordance with a method in the prior art. In this example, an n-type dopant such as phosphorous or arsenic is implanted in substrate 101 to provide background doping. A gate electrode 103 (e.g., polysilicon) is formed on top of a gate dielectric 102 (FIG. 1A), which is formed on top of substrate 101. Using gate electrode 103 for alignment, a p-type dopant such as boron or indium is implanted in substrate 101 to create inactive dopant regions 104 (FIG. 1B). Sidewall spacers 105 (e.g., silicon nitride) are formed adjacent to gate electrode 103 and on top of inactive dopant regions 104 (FIG. 1C) for aligning the implantation of a p-type dopant in substrate 101 and thereby create inactive dopant regions 106 (FIG. ID). Subsequently, source/drain extension (xe2x80x9cSDExe2x80x9d) regions 107 and source/drain (xe2x80x9cSDxe2x80x9d) regions 108 are created (FIG. 1E) by activating inactive dopant regions 104 and 106 by high temperature (e.g., 700xc2x0 C. to 1100xc2x0 C.) rapid thermal annealing. An n-channel MOS transistor can be similarly fabricated using appropriate dopants.
An MOS transistor can also be fabricated using the so-called disposable spacer process illustrated in FIGS. 2A-2C. In FIG. 2A, sidewall spacers 205 are formed adjacent to a gate electrode 203, which overlies a gate dielectric 202. Using sidewall spacers 205 for alignment, a p-type dopant is implanted in a substrate 201 to create inactive dopant regions 206. Sidewall spacers 205 are removed and, subsequently, inactive dopant regions 207 are created by implanting a p-type dopant in substrate 201 using gate electrode 203 for alignment (FIG. 2B). SDE regions 209 and SD regions 208 are created by activating inactive dopant regions 207 and 206, respectively. While the disposable spacer process has known advantages, the added complexity of having to remove sidewall spacers 205 is not desirable in some applications.
The amount of heat which a semiconductor device absorbs during fabrication is referred to as xe2x80x9cthermal budget.xe2x80x9d A transistor with a low thermal budget is advantageous because high temperature processing can cause transient enhanced diffusion (xe2x80x9cTEDxe2x80x9d), which degrades the device""s characteristics.
From the foregoing, it is desirable to have a method for fabricating an MOS transistor with a low thermal budget and without the need to dispose sidewall spacers.
The invention relates to the fabrication of a transistor with a low thermal budget.
In one embodiment, a transistor is fabricated by forming a gate on a semiconductor substrate. A first amorphous region is created by implanting heavy ions in the substrate using the gate for alignment. Dopants are then implanted in the substrate to create a first inactive dopant region. Sidewall spacers, which align subsequent implantation steps, are formed adjacent to the gate. Thereafter, a second amorphous region is created by implanting heavy ions in the substrate. Dopants are implanted in the substrate to create a second inactive dopant region. Dopants in the first and second inactive dopant regions are then activated using a relatively low temperature annealing process to create source/drain and source/drain extension regions. The present invention simplifies the fabrication of a low thermal budget transistor by dispensing with the requirement to remove the sidewall spacers.